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hm51w16165 series hm51w18165 series 16 m edo dram (1-mword 16-bit) 4 k refresh/1 k refresh ade-203-650d (z) rev. 4.0 nov. 1997 description the hitachi hm51w16165 series, hm51w18165 series are cmos dynamic rams organized as 1,048,576-word 16-bit. they employ the most advanced cmos technology for high performance and low power. hm51w16165 series, hm51w18165 series offer extended data out (edo) page mode as a high speed access mode. they have package variations of standard 400-mil 42-pin plastic soj and 400-mil 50-pin plastic tsop. features single 3.3 v ( 0.3 v) access time: 50 ns/60 ns/70 ns (max) power dissipation ? active mode : 396 mw/360mw/324 mw (max) (hm51w16165 series) : 684 mw /612 mw /540 mw (max) (hm51w18165 series) ? standby mode : 7.2 mw (max) : 0.54 mw (max) (l-version) edo page mode capability refresh cycles ? 4096 refresh cycles : 64 ms (hm51w16165 series) : 128 ms (l-version) ? 1024 refresh cycles : 16 ms (hm51w18165 series) : 128 ms (l-version) 4 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh ? self refresh (l-version) 2cas-byte control battery backup operation (l-version)
hm51w16165 series, hm51w18165 series 2 ordering information type no. access time package hm51w16165j-5 hm51w16165j-6 hm51w16165j-7 50 ns 60 ns 70 ns 400-mil 42-pin plastic soj (cp-42d) hm51w16165lj-5 hm51w16165lj-6 hm51w16165lj-7 50 ns 60 ns 70 ns hm51w18165j-5 hm51w18165j-6 hm51w18165j-7 50 ns 60 ns 70 ns hm51w18165lj-5 hm51w18165lj-6 hm51w18165lj-7 50 ns 60 ns 70 ns hm51w16165tt-5 hm51w16165tt-6 hm51w16165tt-7 50 ns 60 ns 70 ns 400-mil 50-pin plastic tsop ii (ttp-50/44dc) hm51w16165ltt-5 hm51w16165ltt-6 hm51w16165ltt-7 50 ns 60 ns 70 ns hm51w18165tt-5 hm51w18165tt-6 HM51W18165TT-7 50 ns 60 ns 70 ns hm51w18165ltt-5 hm51w18165ltt-6 hm51w18165ltt-7 50 ns 60 ns 70 ns
hm51w16165 series, hm51w18165 series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 cc cc cc ss ss ss v i/o15 i/o14 i/o13 i/o12 v i/o11 i/o10 i/o9 i/o8 nc nc lcas ucas oe a9 a8 a7 a6 a5 a4 v v i/o0 i/o1 i/o2 i/o3 v i/o4 i/o5 i/o6 i/o7 nc nc nc we ras a11 a10 a0 a1 a2 a3 v hm51w16165tt/ltt series (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 v i/o0 i/o1 i/o2 i/o3 v i/o4 i/o5 i/o6 i/o7 nc nc we ras a11 a10 a0 a1 a2 a3 v cc cc cc v i/o15 i/o14 i/o13 i/o12 v i/o11 i/o10 i/o9 i/o8 nc lcas ucas oe a9 a8 a7 a6 a5 a4 v ss ss ss hm51w16165j/lj series (top view) pin description pin name function a0 to a11 address input row/refresh address column address a0 to a11 a0 to a7 i/o0 to i/o15 data input/data output ras row address strobe ucas , lcas column address strobe we read/write enable oe output enable v cc power supply v ss ground nc no connection
hm51w16165 series, hm51w18165 series 4 pin arrangement v i/o0 i/o1 i/o2 i/o3 v i/o4 i/o5 i/o6 i/o7 nc nc we ras nc nc a0 a1 a2 a3 v cc cc cc v i/o15 i/o14 i/o13 i/o12 v i/o11 i/o10 i/o9 i/o8 nc lcas ucas oe a9 a8 a7 a6 a5 a4 v ss ss ss hm51w18165j/lj series cc cc cc ss ss ss v i/o15 i/o14 i/o13 i/o12 v i/o11 i/o10 i/o9 i/o8 nc nc lcas ucas oe a9 a8 a7 a6 a5 a4 v v i/o0 i/o1 i/o2 i/o3 v i/o4 i/o5 i/o6 i/o7 nc nc nc we ras nc nc a0 a1 a2 a3 v hm51w18165tt/ltt series 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 (top view) pin description pin name function a0 to a9 address input row/refresh address column address a0 to a9 a0 to a9 i/o0 to i/o15 data input/data output ras row address strobe ucas , lcas column address strobe we read/write enable oe output enable v cc power supply v ss ground nc no connection
hm51w16165 series, hm51w18165 series 5 block diagram (hm51w16165 series) ? ? ? ? ? ? a0 a1 to a7 a10 a11 a8 a9 timing and control ras ucas lcas we oe column address buffers row address buffers i/o buffers i/o0 to i/o15 column decoder row decoder 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array block diagram (hm51w18165 series) ? ? ? ? ? ? a0 a1 to a9 timing and control column address buffers row address buffers i/o buffers i/o0 to i/o15 column decoder row decoder 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array 1m array ras ucas lcas we oe truth table
hm51w16165 series, hm51w18165 series 6 ras lcas ucas we oe output operation h d d d d open standby l l h h l valid lower byte read cycle l h l h l valid upper byte l l l h l valid word llhl* 2 d open lower byte early write cycle lhll* 2 d open upper byte llll* 2 d open word llhl* 2 h undefined lower byte delayed write cycle lhll* 2 h undefined upper byte llll* 2 h undefined word l l h h to l l to h valid lower byte read-modify-write cycle l h l h to l l to h valid upper byte l l l h to l l to h valid word l h h d d open word ras -only refresh cycle h to l h l d d open word cas -before- ras refresh cycle or h to l l h d d open word self refresh cycle (l-version) h to l l l d d open word l l l h h open read cycle (output disabled) notes: 1. h: high (inactive) l: low (active) d: h or l 2. t wcs 3 0 ns early write cycle t wcs < 0 ns delayed write cycle 3. mode is determined by the or function of the ucas and lcas . (mode is set by the earliest of ucas and lcas active edge and reset by the latest of ucas and lcas inactive edge.) however write operation and output hiz control are done independently by each ucas , lcas . ex. if ras = h to l, ucas = h, lcas = l, then cas -before- ras refresh cycle is selected.
hm51w16165 series, hm51w18165 series 7 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C0.5 to v cc + 0.5 ( +4.6 v (max)) v supply voltage relative to v ss v cc C0.5 to +4.6 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit notes supply voltage v cc 3.0 3.3 3.6 v 1, 2 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il C0.3 0.8 v 1 notes: 1. all voltage referred to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
hm51w16165 series, hm51w18165 series 8 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hm51w16165 series) hm51w16165 -5 -6 -7 parameter symbol min max min max min max unit test conditions operating current* 1, * 2 i cc1 110 100 90 ma t rc = min standby current i cc2 2 2 2 ma ttl interface ras , ucas , lcas = v ih dout = high-z 1 1 1 ma cmos interface ras , ucas , lcas 3 v cc C 0.2 v dout = high-z standby current (l-version) i cc2 150 150 150 m a cmos interface ras , ucas , lcas 3 v cc C 0.2 v dout = high-z ras -only refresh current* 2 i cc3 110 100 90 ma t rc = min standby current* 1 i cc5 5 5 5 ma ras = v ih ucas , lcas = v il dout = enable cas -before- ras refresh current i cc6 110 100 90 ma t rc = min edo page mode current* 1, * 3 i cc7 105 95 85 ma t hpc = min battery backup current* 4 (standby with cbr refresh) (l-version) i cc10 400 400 400 m a cmos interface dout = high-z cbr refresh: t rc = 31.3 m s t ras 0.3 m s self refresh mode current (l-version) i cc11 250 250 250 m a cmos interface ras , ucas , lcas 0.2 v dout = high-z input leakage current i li C10 10 C10 10 C10 10 m a 0 v vin 4.6 v output leakage current i lo C10 10 C10 10 C10 10 m a 0 v vout 4.6 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc 2.4 v cc v high iout = C2 ma output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while ucas and lcas = v ih . 4. v ih 3 v cc C 0.2 v, 0 v v il 0.2 v.
hm51w16165 series, hm51w18165 series 9 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hm51w18165 series) hm51w18165 -5 -6 -7 parameter symbol min max min max min max unit test conditions operating current* 1, * 2 i cc1 190 170 150 ma t rc = min standby current i cc2 2 2 2 ma ttl interface ras , ucas , lcas = v ih dout = high-z 1 1 1 ma cmos interface ras , ucas , lcas 3 v cc C 0.2 v dout = high-z standby current (l-version) i cc2 150 150 150 m a cmos interface ras , ucas , lcas 3 v cc C 0.2 v dout = high-z ras -only refresh current* 2 i cc3 190 170 150 ma t rc = min standby current* 1 i cc5 5 5 5 ma ras = v ih ucas , lcas = v il dout = enable cas -before- ras refresh current i cc6 190 170 150 ma t rc = min edo page mode current* 1, * 3 i cc7 185 165 145 ma t hpc = min battery backup current* 4 (standby with cbr refresh) (l-version) i cc10 400 400 400 m a cmos interface dout = high-z cbr refresh: t rc = 125 m s t ras 0.3 m s self refresh mode current (l-version) i cc11 250 250 250 m a cmos interface ras , ucas , lcas 0.2 v dout = high-z input leakage current i li C10 10 C10 10 C10 10 m a 0 v vin 4.6 v output leakage current i lo C10 10 C10 10 C10 10 m a 0 v vout 4.6 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc 2.4 v cc v high iout = C2 ma output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while ucas and lcas = v ih . 4. v ih 3 v cc C 0.2 v, 0 v v il 0.2 v.
hm51w16165 series, hm51w18165 series 10 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol typ max unit notes input capacitance (address) c i1 5 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-in, data-out) c i/o 7 pf 1, 2 notes : 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ras , ucas and lcas = v ih to disable dout.
hm51w16165 series, hm51w18165 series 11 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v)* 1, * 2, * 18, * 19, * 20 test conditions input rise and fall time: 2 ns input levels: 0 v, 3.0 v input timing reference levels: 0.8 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v output load: 1 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) hm51w16165/hm51w18165 -5 -6 -7 parameter symbol min max min max min max unit notes random read or write cycle time t rc 84 104 124 ns ras precharge time t rp 30 40 50 ns cas precharge time t cp 81013ns ras pulse width t ras 50 10000 60 10000 70 10000 ns cas pulse width t cas 8 10000 10 10000 13 10000 ns row address setup time t asr 000ns row address hold time t rah 81010ns column address setup time t asc 000ns21 column address hold time t cah 81013ns21 ras to cas delay time t rcd 12 37 14 45 14 52 ns 3 ras to column address delay time t rad 10 25 12 30 12 35 ns 4 ras hold time t rsh 10 13 13 ns cas hold time t csh 35 40 45 ns 23 cas to ras precharge time t crp 555ns22 oe to din delay time t oed 13 15 18 ns 5 oe delay time from din t dzo 000ns6 cas delay time from din t dzc 000ns6 transition time (rise and fall) t t 250250250ns7
hm51w16165 series, hm51w18165 series 12 read cycle hm51w16165/hm51w18165 -5 -6 -7 parameter symbol min max min max min max unit notes access time from ras t rac 50 60 70 ns 8, 9 access time from cas t cac 13 15 18 ns 9, 10, 17 access time from address t aa 25 30 35 ns 9, 11, 17 access time from oe t oea 131518ns 9 read command setup time t rcs 000ns21 read command hold time to cas t rch 0 0 0 ns 12, 22 read command hold time from ras t rchr 50 60 70 ns read command hold time to ras t rrh 000ns12 column address to ras lead time t ral 25 30 35 ns column address to cas lead time t cal 15 18 23 ns cas to output in low-z t clz 000ns output data hold time t oh 333ns27 output data hold time from oe t oho 333ns output buffer turn-off time t off 13 15 15 ns 13, 27 output buffer turn-off to oe t oez 131515ns 13 cas to din delay time t cdd 13 15 18 ns 5 output data hold time from ras t ohr 333ns27 output buffer turn-off to ras t ofr 131515ns 27 output buffer turn-off to we t wez 131515ns we to din delay time t wed 13 15 18 ns ras to din delay time t rdd 13 15 18 ns ras next cas delay time t rncd 50 60 70 ns
hm51w16165 series, hm51w18165 series 13 write cycle hm51w16165/hm51w18165 -5 -6 -7 parameter symbol min max min max min max unit notes write command setup time t wcs 0 0 0 ns 14, 21 write command hold time t wch 8 10 13 ns 21 write command pulse width t wp 8 10 10 ns write command to ras lead time t rwl 8 10 13 ns write command to cas lead time t cwl 8 10 13 ns 23 data-in setup time t ds 0 0 0 ns 15, 23 data-in hold time t dh 8 10 13 ns 15, 23 read-modify-write cycle hm51w16165/hm51w18165 -5 -6 -7 parameter symbol min max min max min max unit notes read-modify-write cycle time t rwc 111 135 161 ns ras to we delay time t rwd 67 79 92 ns 14 cas to we delay time t cwd 30 34 40 ns 14 column address to we delay time t awd 42 49 57 ns 14 oe hold time from we t oeh 13 15 18 ns refresh cycle hm51w16165/hm51w18165 -5 -6 -7 parameter symbol min max min max min max unit notes cas setup time (cbr refresh cycle) t csr 555ns21 cas hold time (cbr refresh cycle) t chr 8 10 10 ns 22 ras precharge to cas hold time t rpc 555ns21
hm51w16165 series, hm51w18165 series 14 edo page mode cycle hm51w16165/hm51w18165 -5 -6 -7 parameter symbol min max min max min max unit notes edo page mode cycle time t hpc 20 25 30 ns 25 edo page mode ras pulse width t rasp 100000 100000 100000 ns 16 access time from cas precharge t cpa 30 35 40 ns 9, 17, 22 ras hold time from cas precharge t cprh 30 35 40 ns output data hold time from cas low t doh 3 3 3 ns 9 cas hold time referred oe t col 8 10 13 ns cas to oe setup time t cop 5 5 5 ns read command hold time from cas precharge t rchc 30 35 40 ns edo page mode read-modify-write cycle hm51w16165/hm51w18165 -5 -6 -7 parameter symbol min max min max min max unit notes edo page mode read-modify-write cycle time t hprwc 57 68 79 ns we delay time from cas precharge t cpw 45 54 62 ns 14, 22 refresh (hm51w16165 series) parameter symbol max unit note refresh period t ref 64 ms 4096 cycles refresh period (l-version) t ref 128 ms 4096 cycles refresh (hm51w18165 series) parameter symbol max unit note refresh period t ref 16 ms 1024 cycles refresh period (l-version) t ref 128 ms 1024 cycles
hm51w16165 series, hm51w18165 series 15 self refresh mode (l-version) hm51w16165l/hm51w18165l -5 -6 -7 parameter symbol min max min max min max unit notes ras pulse width (self refresh) t rass 100 100 100 m s 28, 29, 30, 31 ras precharge time (self refresh) t rps 90 110 130 ns cas hold time (self refresh) t chs C50 C50 C50 ns notes: 1. ac measurements assume t t = 2 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd 3 t rad (max) + t aa (max) C t cac (max), then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl loads and 100 pf. 10. assumes that t rcd 3 t rcd (max) and t rcd + t cac (max) 3 t rad + t aa (max). 11. assumes that t rad 3 t rad (max) and t rcd + t cac (max) t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. these parameters are referred to ucas and lcas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. 16. t rasp defines ras pulse width in edo page mode cycles. 17. access time is determined by the longest among t aa , t cac and t cpa . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device 19. when both ucas and lcas go low at the same time, all 16-bit data are written into the device. ucas and lcas cannot be staggered within the same write/read cycles. 20 all the v cc and v ss pins shall be supplied with the same voltages.
hm51w16165 series, hm51w18165 series 16 21. t asc , t cah , t rcs , t wcs , t wch , t csr and t rpc are determined by the earlier falling edge of ucas or lcas . 22. t crp , t chr , t rch , t cpa and t cpw are determined by the later rising edge of ucas or lcas . 23. t cwl , t dh , t ds and t chs should be satisfied by both ucas and lcas . 24. t cp is determined by the time that both ucas and lcas are high. 25. t hpc (min) can be achieved during a series of edo page mode write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle (t cas + t cp + 2 t t ) becomes greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2). 26. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 27. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off . 28. please do not use t rass timing, 10 m s t rass 100 m s. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass 3 100 m s, then ras precharge time should use t rps instead of t rp . 29. if you use distributed cbr refresh mode with 15.6 m s interval in normal read/write cycle, cbr refresh should be executed within 15.6 m s immediately after exiting from and before entering into self refresh mode. 30. if you use ras only refresh or cbr burst refresh mode in normal read/write cycle, 4096 or 1024 cycles (4096 cycles: hm51w16165 series, 1024 cycles: hm51w18165 series) of distributed cbr refresh with 15.6 m s interval should be executed within 64 or 16 ms (64 ms: hm51w16165, 16 ms: hm51w18165) immediately after exiting from and before entering into the self refresh mode. 31. repetitive self refresh mode without refreshing all memory is not allowed. once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 32. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hm51w16165 series, hm51w18165 series 17 notes concerning 2 cas control please do not separate the ucas / lcas operation timing intentionally. however skew between ucas / lcas are allowed under the following conditions. 1. each of the ucas / lcas should satisfy the timing specifications individually. 2. different operation mode for upper/lower byte is not allowed; such as following. ras ucas lcas we delayed write early write 3. closely separated upper/lower byte control is not allowed. however when the condition (t cp t ul ) is satisfied, edo page mode can be performed. ras ucas lcas t ul 4. byte control operation by remaining ucas or lcas high is guaranteed.
hm51w16165 series, hm51w18165 series 18 timing waveforms * 32 read cycle ras address we dout oe din t rc t ras t rp t csh t crp t rcd t rsh t cas t t t rad t ral t cal t asc t cah t asr row column t rah t rcs t rch t rrh t cdd t dzc high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez ucas lcas t rdd t wed t ofr t ohr t wez t rchr
hm51w16165 series, hm51w18165 series 19 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t ucas lcas
hm51w16165 series, hm51w18165 series 20 delayed write cycle * 18 address ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t oed t oeh t clz t oez invalid dout high-z din high-z ucas lcas
hm51w16165 series, hm51w18165 series 21 read-modify-write cycle * 18 address ras din dout oe we t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t oed t oeh t oea t cac t aa t rac t oho t oez t clz dout high-z ucas lcas
hm51w16165 series, hm51w18165 series 22 ras -only refresh cycle ras address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off t ofr ucas lcas
hm51w16165 series, hm51w18165 series 23 cas -before- ras refresh cycle ras address dout high-z t off t ofr t cp t rpc t csr t chr t cp t rpc t csr t chr t crp t rp t ras t rc t rc t rp t ras t rp t t ucas lcas
hm51w16165 series, hm51w18165 series 24 hidden refresh cycle din oe dout we address ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rcd t rsh t chr t crp t rad t ral t cah t asc t rah t asr t t cdd t dzc dzo t oed t oez t oho t off t oh t cac t aa t rac t clz t dout column row oea t high-z t rch t rrh ucas lcas t wed t rdd wez t ofr t ohr t rcs
hm51w16165 series, hm51w18165 series 25 edo page mode read cycle din oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t cac t cpa t t oez t oea t oez t aa t cac t t rasp cop t rp t cas t cas t cas t cal t csh t rncd t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 2 dout 4 dout 1 t cas t rcs t t rcs dout 3 t oho t t cprh t hpc t oea t wez dzo t oed oho doh rch t rchr t cal t cal t cal t rsh t rchc cpa asc
hm51w16165 series, hm51w18165 series 26 edo page mode read cycle (2 cas control) oe we address t dzc t cdd t rdd high-z t ofr t oez t oho t off t oh t ohr t t col t t cpa t aa t cac t cac t oea t aa t rac t aa t doh t t oez t t oez t aa t cac t cop t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 4 dout 1 t rcs t oho t oea dzo t oed t cac t rchc cpa asc ras ucas lcas t cp t cp t cp t t t rch t rrh t rasp t rp t cas t cas t cas t csh t hpc t hpc t hpc crp t t cas t rncd t rsh l dout u dout dout 1 dout 3 dout 2 oho oea dout 4 t cpa t cal cal cal t t cal t din
hm51w16165 series, hm51w18165 series 27 edo page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n ucas lcas
hm51w16165 series, hm51w18165 series 28 edo page mode delayed write cycle * 18 we din oe dout address ras t rasp t rp t crp t rsh t cas t hpc t cas t cas t csh t rcd t t t cp t cp t asc t cah t asc t cah t asc t cah t rad t asr t rah t rcs t rcs t rcs t rwl t cwl t cwl t cwl t wp t wp t wp t dzc t ds t dzc t ds t ds t dzc t dh t dh t dh t dzo t oed t dzo t oed t dzo t oed t oeh t oeh t oeh t oez t clz t clz t oez t clz t oez invalid dout invalid dout invalid dout din 1 din 2 din n column n column 2 column 1 row high-z ucas lcas
hm51w16165 series, hm51w18165 series 29 edo page mode read-modify-write cycle * 18 we din oe dout address ras t rasp t crp t cp t hprwc t t t rcd t cas t cp t cas t cas t rad t asr t asc t asc t asc t rah t cah t cah t cah t cwl t cpw t cwl t cpw t cwl t rwd t awd t awd t awd t cwd t rcs t cwd t rcs t cwd t rcs t wp t wp t wp t ds t dzc t ds t dzc t ds t dzc t dh t dh t dh t dzo t dzo t dzo t oeh t oeh t oeh t aa t rac t oez t clz dout n dout 2 dout 1 din 1 din 2 din n column n column 2 column 1 t rp row t rwl t oho t oea t cac t oez t clz t oho t oea t cac t cpa t oez t clz t oho t oea t cac t cpa high-z t oed t oed t oed aa t aa t t rsh ucas lcas
hm51w16165 series, hm51w18165 series 30 edo page mode mix cycle (1) oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t cpa t oez t aa t oea t t rasp t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal row dout 2 dout 4 cpa t cas t wcs dout 3 t t t wp t wch t wed t wez t ds t dh t ds t dh din 3 din 1 t oea t oed t cac t asc t cpw t awd oho t cal t rcs t rcs t csh t rcd t rsh doh asc t din
hm51w16165 series, hm51w18165 series 31 edo page mode mix cycle (2) din oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t oez t oho t off t oh t cpa t aa t cac t aa t cac t oez t t oea t t rasp t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t rcs row dout 1 dout 4 cpa t cas dout 3 t oho t wed t wez t ds t dh t ds t din 3 din 2 t oea t t cac t cpw t rch t rcs t wch t rac t oed t col t oea t oho t oez t dh oed t rcs t rncd t cal t cal t cal t rcd t rchr t wcs t rsh t wp t asc aa cop
hm51w16165 series, hm51w18165 series 32 self refresh cycle (l-version)* 28, * 29, * 30, * 31 ras dout t rp t rass t rps t rpc t t t cp t csr t chs t crp t off t ofr high-z ucas lcas
hm51w16165 series, hm51w18165 series 33 package dimensions hm51w16165j/lj series hm51w18165j/lj series (cp-42d) 9.40 0.25 1 21 0.43 0.10 3.50 0.26 22 42 27.43 max 27.06 0.74 10.16 0.13 11.18 0.13 0.10 1.30 max 2.50 0.12 1.27 0.80 +0.25 ?.17 hitachi code jedec eiaj weight (reference value) cp-42d conforms 1.75 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension
hm51w16165 series, hm51w18165 series 34 hm51w16165tt/ltt series hm51w18165tt/ltt series (ttp-50/44dc) 0.13 m 0.10 0.80 50 26 125 20.95 21.35 max 0.27 0.07 1.20 max 10.16 0.13 0.05 11.76 0.20 0 ?5 1.15 max 0.145 0.05 40 36 11 15 3.20 0.50 0.10 0.68 0.80 hitachi code jedec eiaj weight (reference value) ttp-50/44dc conforms ? 0.50 g 0.25 0.05 0.125 0.04 unit: mm dimension including the plating thickness base material dimension
hm51w16165 series, hm51w18165 series 35 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm51w16165 series, hm51w18165 series 36 revision record rev. date contents of modification drawn by approved by 1.0 sep. 30, 1996 initial issue y. kasama m. mishima 2.0 nov. 28, 1996 addition of hm51w16165/hm51w18165-5 series power dissipation (active) 468/414 mw(max) to 396/360/324 mw (max) (hm51w16165 series) 666/594 mw(max) to 684/612/540 mw (max) (hm51w18165 series) dc characteristics (hm51w16165 series) i cc7 max: 135/115 ma to 105/95/85 ma dc characteristics (hm51w18165 series) i cc7 max: 185/165 ma to 185/165/145 ma ac characteristics t rcd min: 20/20 ns to 12/14/14 ns t rad min: 15/15 ns to 10/12/12 ns t rsh min: 15/18 ns to 10/13/13 ns t rrh min: 0/0 ns to 5/5/5 ns t rwc min: 136/161 ns to 111/135/161 ns t rpc min: 0/0 ns to 5/5/5 ns timing waveforms addition of t rncd timing to edo page mode mix cycle (2) y. kasama m. mishima 3.0 feb. 24, 1997 ac characteristics t rrh min: 5/5/5 ns to 0/0/0 ns y. kasama y. matsuno 4.0 nov. 1997 change of subtitle

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